The present invention pertains to a secure communications system and more particularly to a processor architecture having a single control element which provides control of data transfer between cypher text data memory (black) and plain text data memory (red).
Modern day communications systems are controlled by central processing units (CPU). These CPUs or processors control the flow of data within the system. Secure processor arrangements have previously included separate processors, one for each kind of data (red and black). A red processor worked with the red data memory and a black processor worked with the black data memory. When data is to be exchanged, for encrypting or decrypting, an elaborate data transfer was required. The data transfer was a series of messages exchanged between the red and black processors. The data was sent to the encrypt/decrypt function and did not pass through the processors. As a result the red processor handles only red (unencrypted or plain text messages) data and the black processor handles only black data (encrypted or cypher text messages).
The two processors required to handle data under the previous system were an implementation of the two man security rule. In the two processor system, a failure in either processor would not compromise security. That is, secure data could not be compromised, if only one of the processors were found to be compromised. Further, since two processors require two bus structures, there are more places where security failures may occur.
Accordingly, it is an object of the present invention to provide single controlling processor for a secure red/black memory system which provides equivalent assurances to the two man security rule while minimizing the amount of circuitry and the number of places which are susceptible to security failure.